In many computer-aided applications it is necessary to exchange data between two integrated chips situated on the motherboard of a computer. Thus, by way of example, data has to be transferred bidirectionally between the processor and an integrated semiconductor memory, for example a DRAM (dynamic random access memory) semiconductor memory. In order to store data signals that are transferred from the processor to the DRAM memory via a databus in memory cells of the integrated semiconductor memory, the incoming data signals have to be amplified by the integrated semiconductor memory prior to further processing.
For this purpose, the integrated semiconductor memory generally has an input amplifier that amplifies incoming data signals to a defined level. The bit lines connected to the memory cells are driven with this amplified level. For example, in an integrated semiconductor memory having a low voltage level of 1 V for an incoming data signal, the voltage level may be attenuated to an output level of, e.g., 0 V. A high voltage level of a data signal, for example a voltage level of 1.45 V, is amplified to a high output level of 2.5 V, for example. The bit lines connected to the memory cells in which the data signals are intended to be stored are driven with the low or high voltage level, respectively, by the input amplifier. Particularly in the case of an integrated semiconductor memory, a differential amplifier circuit is generally used as input amplifier.
FIG. 7 depicts a known circuit of a differential amplifier in CMOS technology such as is generally used as an input amplifier for an integrated semiconductor memory. Connected between a terminal VA for application of a supply potential VDD and a terminal VB for application of a reference potential VSS are a current mirror circuit 1 as active load, which includes two transistors T1 and T2, a transistor T3 for application of an input signal Vin′, a transistor T4 for application of a reference signal Vref′ and a current mirror circuit 2 for generating the source summation current ISS. The current mirror circuit 2 is connected via a resistor R to the terminal VA for application of the supply potential VDD and includes two transistors T5 and T6. For the purpose of generating an output signal Vout′, the input terminal E1′, which represents the control terminal of the transistor T3, is driven with the input signal Vin′. A second input terminal E2′, which forms the control terminal of the transistor T4, is driven with the reference signal Vref′. With correct dimensioning of the transistors T1, . . . , T6, the differential amplifier circuit generates the output signal Vout′ with a high level if the level of the input signal Vin′ lies above the level of the reference signal Vref′. Conversely, the differential amplifier circuit generates the output signal Vout′ with a low level if the input signal Vin′ lies below the level of the reference signal Vref′.
Data transfer rates, particularly in CMOS technology, have continually increased in recent years. In order to meet the high speed requirements, the source summation current ISS, which is fed into the two parallel branches of the differential amplifier by the current mirror circuit 2 acting as a current source, has to be increased further and further. The present high speed requirements thus cause an extreme rise in the current consumption of the differential amplifier in CMOS technology used as an input amplifier. A low current consumption is generally of interest, however.
A further difficulty in the use of a conventional differential amplifier as an input amplifier of an integrated semiconductor memory arises from the fact that the supply voltages that are available on the motherboard of a computer are decreasing further and further. Consequently, it is becoming more and more difficult to operate the transistors T1, . . . , T6 connected between the supply potential and the reference potential. In addition to the drain-source voltage drops at these transistors, the threshold voltages of the transistors also pose a problem, in particular, since they cannot be scaled with the decreasing supply voltages. The consequence is that three transistors in series, such as, for example, the transistors T1 and T2 of the active load 1, the input transistors T3 and T4, respectively, and the transistors of the current mirror circuit 2, can no longer be driven, or can be driven only with very great difficulty, between the high supply potential VDD and the reference potential VSS.
As described above, the differential amplifier compares a high or low level of the input signal Vin′ with the level of the reference signal Vref′. The operating point of the differential amplifier circuit is set in such a way that, at a level of the reference signal Vref′ that lies precisely in the middle between a possible high or low level of the input signal Vin′, the differential amplifier circuit generates, on the output side, the output signal Vout′ with an amplified high or low output level matched to the downstream circuit stages. The small supply voltages or the tolerances of resistors of a voltage divider from which the potential of the reference voltage is generally generated have the effect, however, that the level of the reference signal Vref′ cannot be set precisely to the middle level between the high voltage potential and the low voltage potential of the input signal Vin′. On account of this inaccuracy with which the reference level can be set, the differential amplifier circuit very easily drifts from its operating point.
A further problem occurs by virtue of the fact that in general not every input signal Vin′ is coupled to a dedicated reference signal Vref′ in the case of a differential amplifier as an input amplifier of an integrated semiconductor memory in CMOS technology. This has the effect that a noise signal superposed on the input signal is not simultaneously superposed on the reference signal as well. Consequently, the advantage of a high common-mode rejection, such as in the case of ECL logic for instance, is not afforded in the case of a differential amplifier in CMOS technology.
It has furthermore been shown that fluctuations of the reference voltage Vref′ entail large deviations in the duty cycle. The duty cycle specifies how an input signal is temporally mapped into an output signal at the output terminal of the differential amplifier. The imprecise setting of the reference voltage ultimately has the effect that the temporal length of an input signal pulse does not correlate with the length of an output signal pulse. Signal distortions at the output terminal of the differential amplifier are the consequence.
The disadvantages described above have the effect that a conventional differential amplifier circuit becomes less and less usable as an input amplifier of an integrated semiconductor memory.